SK

Lorenz Attractor VGA Display Project

Developing a ASIC design that generate a VGA signal to display the Lorenz Attractor equations on a monitor. The project involves creating a custom hardware design using Verilog, FGPAs, and eventually ASICs to render the system in real-time.

Completed Steps

  • Calculating Lorenz Attractor values (x,y coordinates) using Verilog and exporting to a .csv file.
  • Basic VGA signal output using Arty S7-50 and Digilent VGA PMOD.
  • Plotting Lorenz Attractor .csv file using software for comparison point when plotting with hardware.

In Progress Steps

  • Hardware computing of Lorenz Attractor on Arty S7-50 and storing values within FGPA.
  • Hardware plotting of values over VGA.

Technologies Used

FGPA DesignASIC DesignHardware DesignVerilogVerification Engineering