Lorenz Attractor VGA Display Project
A custom hardware design that generates a VGA signal to display the Lorenz Attractor equations on a monitor. Built in Verilog, the design computes and plots the system in real time on an FPGA, and is now being taped out as an ASIC.
Completed Steps
- Calculating Lorenz Attractor values (x,y coordinates) using Verilog and exporting to a .csv file.
- Basic VGA signal output using Arty S7-50 and Digilent VGA PMOD.
- Plotting Lorenz Attractor .csv file using software for comparison point when plotting with hardware.
- Hardware computing of Lorenz Attractor on Arty S7-50 and storing values within FPGA.
- Hardware plotting of values over VGA.
In Progress Steps
- Taping out the design as an ASIC.
Technologies Used
FPGA DesignASIC DesignHardware DesignVerilogVerification Engineering